1. Field of the Invention
The present invention relates to sigma-delta digital to analog converters (DACs), and more particularly to methods and apparatuses for mismatch shaping of an oversampled converter. Even more specifically, the present invention relates to mismatch shaping networks for use in multi-bit DACs.
2. Background Art
It is known to process analog signals using digital circuitry. Typically, such circuitry converts analog signal to binary values, arithmetically manipulates the binary values with binary circuitry to perform filtering and digital signal processing, and then converts the processed binary values back into analog signals (e.g., for sound reproduction). To minimize the circuitry required to convert the analog signals to binary values, sigma-delta modulators are often utilized.
Sigma-delta modulators sample the analog signal at a rate that is orders of magnitude greater than the highest frequency present. Sigma-delta modulators use the technique of oversampling and noise shaping to move most of the quantization noise outside the band of the signal. The out of band noise may then be filtered out such that the signal to noise ratio (SNR) within the signal band is significantly increased.
The use of a multi-bit sigma-delta DAC lowers the in-band and out of band quantization noise as compared to single bit modulators with single bit DACs. However, multi-bit modulators typically require multi-bit DACs with highly linear performance. The linearity of a multi-bit DAC is typically limited by how precise analog elements, such as capacitors, resistors or current sources, can be matched. The linearity performance of analog components fabricated with standard CMOS techniques is less than 13 bits. Therefore, mismatch shaping circuitry is often utilized to improve the linearity performance of the analog components. Mismatch shaping circuitry shapes the mismatches in the analog unit elements to substantially reduce errors in the signal band of an oversampling converter.
A method and apparatus for performing dynamic element matching is disclosed in Leung, U.S. Pat. No. 5,406,283, entitled “Multi-bit oversampled DAC with dynamic element matching.” The Leung patent discloses a technique for cyclically selecting successive different permutations of the unit elements for converting each value of the output digital signal thereby canceling the mismatching between unit elements. However, the digital complexity of such a method increases tremendously with the number of bits in the digital output. For example, a typical implementation of such a system requires an encoder for each value of output digital signal, a memory element or pointer for each digital value and a M×M cross-point switch, where M is the number of unit elements. Therefore, as the number of unit elements doubles the encoder and memory elements required increases by a factor of two but the cross-point switch complexity and hardware increases by a factor of four, or more generally as a square term.
In addition, there is a possibility for pattern noise to occur since the unit elements are cyclically selected. For example, if the same code is output each time and if there are mismatches on the unit elements, a spur may occur at a frequency given by the inverse of the cyclical selection period.
Therefore, it would be advantageous to provide a method and apparatus for mismatch shaping of oversampled data converters that does not suffer from the above described design complexity and pattern noise errors.